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FAST CMOS BUFFER/CLOCK DRIVER
Integrated Device Technology, Inc.
IDT49FCT805/A IDT49FCT806/A
FEATURES:
* * * * * * * * * * * 0.5 MICRON CMOS Technology Guaranteed low skew < 700ps (max.) Low duty cycle distortion < 1ns (max.) Low CMOS power levels TTL compatible inputs and outputs Rail-to-rail output voltage swing High drive: -24mA IOH, 64mA IOL Two independent output banks with 3-state control 1:5 fanout per bank `Heartbeat' monitor output Available in DIP, SOIC, SSOP (805 only), QSOP (805 only), Cerpack and LCC packages * Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT49FCT805/A and IDT49FCT806/A are clock drivers built using advanced dual metal CMOS technology. The IDT49FCT805/A is a non-inverting clock driver and the IDT49FCT806/A is an inverting clock driver. Each device consists of two banks of drivers. Each bank drives five output buffers from a standard TTL compatible input. The devices feature a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The IDT49FCT805/A and IDT49FCT806/A offer low capacitance inputs with hysteresis. Rail-to-rail output swing improves noise margin and allows easy interface with CMOS inputs.
FUNCTIONAL BLOCK DIAGRAMS
IDT49FCT805
OEA
IDT49FCT806
OEA
INA
5
OA1-OA5
INA
5
OA1-OA5
INB
5
OB1-OB5
INB
5
OB1-OB5
OEB MON
OEB MON
2574 drw 01
2574 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
SEPTEMBER 1996
DSC-2574/10
9.1
1
IDT49FCT805/806/A FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT49FCT805
VCCA VCCB OA2 OA1
VCCA OA1 OA2 OA3 GNDA OA4 OA5 NC (1) OEA INA 1 2 3 4 5 6 7 8 9 10 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 20 19 18 17 16 15 14 13 12 11 VCCB OB1 OB2 OB3 GNDB OB4 OB5 MON
INDEX
3 OA3 GNDA OA4 OA5 NC
(1)
2
4 5 6 7 8
1
20 19 18 17 OB2 OB3 GNDB OB4 OB5
L20-2
OB1
16 15 14
9 10 11 12 13
OEA
INA
INB
OEB
OEB INB
LCC TOP VIEW
MON
2574 drw 04
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW 2574 drw 03
IDT49FCT806
VCCA OA1 OA2 OA3 GNDA OA4 OA5 NC (1) OEA INA 1 2 3 4 5 6 7 8 9 10 P20-1 D20-1 SO20-2 & E20-1 20 19 18 17 16 15 14 13 12 11
VCCA VCCB
VCCB
OA1
OB1 OB2
3
2 1
20 19 18 17 L20-2 16 15 14 OB2 OB3 GNDB OB4 OB5
OB3 GNDB OB4 OB5 MON OEB INB
OA3 GNDA OA4 OA5 NC (1)
4 5 6 7 8 9
OEA
10 11 12 13
OEB MON
2574 drw 06
INA
LCC TOP VIEW
DIP/SOIC/CERPACK TOP VIEW
2574 drw 05
PIN DESCRIPTION
OEA, OEB
INA, INB OAn, OBn
Pin Names
Description 3-State Output Enable Inputs (Active LOW) Clock Inputs Clock Outputs (FCT805) Clock Outputs (FCT806) Monitor Output (FCT805) Monitor Output (FCT806
OAn, OBn
MON
MON
NOTE: 2574 tbl 01 1. Pin 8 is not internally connected on devices with a "K" prefix in the date code. On older devices, pin 8 is internally connected to GND. To insure compatibility with all products, pin 8 should be connected to GND at the board level.
9.1
INB
OB1
INDEX
OA2
2
IDT49FCT805/806/A FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM(2) Terminal Voltage with Respect to GND (3) Terminal Voltage with Respect to VTERM GND TSTG Storage Temperature IOUT DC Output Current Max. -0.5 to +7.0 -0.5 to VCC +0.5 -65 to +150 -60 to +120 Unit V V C mA
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 4.5 5.5 Max. Unit 6.0 pF 8.0
pF
2574 lnk 04 NOTE: 1. This parameter is measured at characterization but not tested.
2574 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals. 3. Output and I/O terminals.
FUNCTION TABLE(1)
Outputs Inputs 49FCT805 MON L H L H L H L H L H Z Z 49FCT806
OE OE OEA, OEB
L L H H
INA, INB OAn, OBn
OA OB OAn, OBn
H L Z Z
MON
H L H L
2574 tbl 02
NOTE: 1. H = HIGH, L = LOW, Z = High Impedance
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL VIK IOS VOH Parameter Input HIGH Level Input LOW Level Input HIGH Current (5) Input LOW Current (5) Off State (HIGH Z)(5) Output Current (5) Clamp Diode Voltage Short Circuit Current Output HIGH Voltage VCC = Min., IIN= -18mA VCC = Max.(3) , VO = GND IOH = -300A VCC = 3V, VIN = VLC or VHC, IOH = -32A VCC = Min. VIN = VIH or VIL IOH = -12mA MIL. IOH = -15mA COM'L. IOH = -24mA MIL. IOH = -24mA COM'L. VCC = 3V, VIN = VLC or VHC, IOL= 300A VCC = Min. VIN = VIH or VIL
VH
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max. VI = VCC VI = GND VO = VCC VO = GND
Min. 2.0 -- -- -- -- -- -- -60 VHC VHC 3.6 2.4 -- -- -- -- --
Typ.(2) -- -- -- -- -- -- -0.7 -120 VCC VCC 4.3 3.8 GND GND 0.3 200 5
Max. -- 0.8 1 1 1 1 -1.2 -- -- -- -- -- VLC VLC(4) 0.55 -- 500
Unit V V A A A A V mA V
VOL
Output LOW Voltage
V
IOH = 300A IOL = 48mA MIL. IOL = 64mA COM'L. --
Input Hysteresis for all inputs Quiescent Power Supply Current
mV A
2574 tbl 05
ICC
VCC = Max., VIN = GND or VCC
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. The test limit for this parameter is 5A at TA = -55C.
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IDT49FCT805/806/A FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OEA = OEB = GND 50% Duty Cycle VCC = Max. Outputs Open fo= 10MHz 50% Duty Cycle OEA = OEB =VCC Mon. Output Toggling VCC = Max. Outputs Open fo = 2.5MHz 50% Duty Cycle OEA = OEB = GND Eleven Outputs Toggling VIN = VCC VIN = GND Test Conditions(1) Min. -- -- Typ.(2) 1.0 0.15 Max. 2.5 0.20 Unit mA mA/ MHz/bit
IC
Total Power Supply Current (6)
VIN = VCC VIN = GND VIN = 3.4V VIN = GND VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
1.5
2.5
mA
--
2.0
3.8
--
4.1
6.0 (5)
--
5.1
8.5 (5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input; (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO= Output Frequency NO= Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz.
2574 tbl 06
9.1
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IDT49FCT805/806/A FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
IDT49FCT805/806 Com'l. Symbol Parameter tPLH Propagation Delay tPHL INA to OAn, INB to OBn tR tF tSK(o) tSK(p) tSK(t) Output Rise Time Output Fall Time Output skew: skew between outputs of all banks of same package (inputs tied together) Pulse skew: skew between opposite transitions of same output (|tPHL-tPLH|) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade Output Enable Time OEA to OAn, OEB to OBn Output Disable Time OEA to OAn, OEB to OBn Mil. IDT49FCT805A/806A Com'l. Mil. Unit ns ns ns ns ns ns
Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. 1.5 5.6 1.5 6.3 1.5 5.3 1.5 6.0 CL = 50pF RL = 500 -- -- -- -- -- 1.5 1.5 0.7 1.0 1.5 -- -- -- -- -- 1.5 1.5 0.9 1.1 1.5 -- -- -- -- -- 1.5 1.5 0.7 1.0 1.5 -- -- -- -- -- 1.5 1.5 0.9 1.1 1.5
tPZL tPZH tPLZ tPHZ
1.5 1.5
8.0 7.0
1.5 1.5
8.5 7.5
1.5 1.5
8.0 7.0
1.5 1.5
8.5 7.5
ns ns
2574 tbl 07 NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.
9.1
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IDT49FCT805/806/A FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 VIN Pulse Generator RT D.U.T. 50pF CL
2574 drw 07
ENABLE AND DISABLE TIME SWITCH POSITION
7.0V
V OUT
Test Disable LOW Enable LOW Disable HIGH Enable HIGH
Switch Closed Open
500
2574 lnk 11 DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
PACKAGE DELAY
3V 1.5V INPUT tPLH tPHL VOH 2.0V OUTPUT tR tF 0.8V 1.5V VOL 0V
OUTPUT SKEW - tSK(o)
INPUT 3V 1.5V 0V VOH 1.5V VOL tSK(o) OUTPUT 2 tPLH2 tPHL2
2574 drw 09
tPLH1
tPHL1
OUTPUT 1 tSK(o)
VOH 1.5V VOL
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
2574 drw 08
PULSE SKEW - tSK(p)
3V 1.5V 0V tPLH tPHL VOH 1.5V VOL
2574 drw 10
PACKAGE SKEW - tSK(t)
INPUT 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL
tPLH1
tPHL1
INPUT
PACKAGE 1 OUTPUT tSK(t) PACKAGE 2 OUTPUT tSK(t)
OUTPUT tSK(p) = |tPHL - tPLH|
tPLH2
tPHL2
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Package 1 and Package 2 are same device type and speed grade
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT t OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH
PZL
2574 drw 11
DISABLE 3V 1.5V 0V t PLZ 3.5V 1.5V t 1.5V 0V 0V
2574 drw 12
SWITCH CLOSED t PZH SWITCH OPEN
3.5V 0.3V V OL
PHZ
0.3V VOH
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: f 1.0MHz; tF 2.5ns; tR 2.5ns
9.1
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IDT49FCT805/806/A FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT49FCT XXX Device Type XX Package X Process/ Temperature Range Blank B P D E L SO PY Q 805 806 805A 806A Commercial (0C to +70C) MIL-STD-883, Class B (-55C to +125C) Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC Shrink Small Outline IC Quarter-size Small Outline IC Non-Inverting Buffer/Clock Driver Inverting Buffer/Clock Driver
2574 drw 17
9.1
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